As the semiconductor industry approaches scaling limits for CMOS processes and technology, integrated circuit manufacturers are rigorously evaluating different types of ultra thin-body transistor structures. As a result of these efforts, it is expected that some non-classical transistor structures will become far more widely accepted and in use. This increasing popularity will be due to their exhibiting higher performance with lower leakage than that which traditional scaled CMOS approaches demonstrate. Double-gated and ultra thin-body MOSFETs offer paths to further scaling. Double-gated transistors, for example, allow twice the drive current, with an inherent coupling between the gates and channel that makes the design more scalable.
At reduced gate lengths, these types of devices have difficulty in maintaining high drive currents (Ion) with low leakage (Ioff) while not demonstrating short-channel effects such as leakage and threshold voltage stability. Bulk silicon planar CMOS devices typically overcome these problems by scaling polysilicon gates and oxides, using super-steep retrograde wells (often triple wells), abrupt source/drain junctions and highly-doped channels. At some point, however, intense channel doping begins to degrade carrier mobility and junction characteristics.
To fabricate devices beyond current scaling limits, integrated circuit designers simultaneously seek to push the planar, bulk silicon CMOS design while exploring alternative gate stack materials, band engineering methods (such as using strained Si or SiGe), and alternative transistor structures.
The double-gated MOSFET provides a particularly promising candidate for ultimate CMOS scaling, due to its better control of near-ideal sub-threshold slope and mobility enhancement. The two gates control roughly twice as much current as a single gate, which allows them to produce significantly stronger switching signals. The two-gate design provides inherent electrostatic and hot-carrier coupling in the channel. This intimate coupling between the gates and channel makes double-gated MOSFET technology one of the most scalable of all FET designs. A significant limitation of this technology, however, relates to the inability of these designs to obtain suitable threshold voltages for high-speed logic devices while controlling extrinsic resistance.
One approach to addressing this limitation, known as a “FinFET,” provides a type of double-gated MOSFET device wherein the gate structure wraps around a thin silicon body (forming the “fin”). The FinFET includes a forward protruding source and an asymmetrically protruding drain behind the gate.
Of the different double-gated approaches a designer might use, the FinFET is one of the easiest to fabricate. Unfortunately, known FinFET fabrication processes require the use of an expensive SOI substrate. The requirement of an SOI substrate poses two significant limitations. First of all, using the comparatively more expensive SOI substrate adds significant costs to the device fabrication process. Secondly, processing the FinFET device over an SOI substrate can yield only a single-layer device. Accordingly, the previously mentioned scaling limitations soon re-emerge. This is because lithographic limits soon constrain the dimensions of features that may be used on the single-layer SOI substrate.